1. Technical Field
The present invention relates to a semiconductor memory apparatus, and more particularly, to a parallel test circuit and a method of performing parallel testing of semiconductor memory is apparatus.
2. Related Art
When fabricating a semiconductor memory apparatus, a test is performed to check whether a plurality of memory cells operate normally. The memory cell test may be performed at various levels, and are roughly divided into a test at a wafer level and a test at a package level.
At the wafer level, input/output terminals are exposed. Therefore, a plurality of memory banks may be simultaneously tested through a probe test. On the other hand, at the package level, memory cells may be accessed only through an input/output pad. Therefore, a plurality of memory banks may be sequentially tested.
FIG. 1 is a schematic block diagram illustrating the configuration of a conventional semiconductor memory apparatus.
The memory apparatus includes a plurality of memory banks and an input/output pad DQ<0:7> configured to input/output data stored in the memory banks. FIG. 1 representatively illustrates a first memory bank 100.
The first memory bank 100 is divided into a first sub bank 10 and a second sub bank 20, in order to efficiently store and access data. The first sub bank 10 and the second sub bank 20 are connected to the input/output pad DQ<0:7> through a global line GIO<0:63>. Since the first and second sub banks 10 and 20 are enabled at different timings during a normal operation, the first and second sub banks 10 and 20 may respectively process data through the shared global line GIO<0:63>. Furthermore, the first and second sub banks 10 and 20 may include test global lines TGIO0<0:63> and TGIO1<0:63>, respectively, which are used during a probe test. The test global lines TGIO0<0:63> and TGIO1<0:63> are provided in local areas of the respective sub banks, and are not connected to the input/output pad during packaging.
At the wafer level, the respective test global lines TGIO0<0:63> and TGIO1<0:63> may be probed to perform a memory cell test.
On the other hand, at the package level, memory cells may be accessed only through the input/output pad DQ<0:7>, and the sub banks share the global line GIO<0:63>. Therefore, a test should be performed for each sub bank sequentially. Therefore, at the package level, it takes a long time to perform a memory cell test.